The present invention relates to interconnect structures for semiconductor chips which employ Group VIII metals, such as palladium, platinum or nickel (Pd, Pt or Ni).
In the present state of the art of semiconductor fabrication, the chip or wafer formation process is completely separate from the interconnect formation process because of the incompatibility of the two processes. This is because the metal interconnects which are formed on the silicon chips for lead soldering are usually made of noble metals, including copper and gold, for example. Noble metals create an unwanted density of states within the band gaps of silicon and are therefore usually not allowed in the semiconductor fabrication facility's clean rooms where the silicon chips are formed. As a result, the interconnect formation and packaging of the silicon chips must be performed at a different manufacturing site which creates the need for additional clean rooms and therefore increases the packaging cost. This has also caused the thin film packaging process and equipment set to become dependent on, and compatible with, the standards set by the semiconductor chip fabrication facility. For example, the fabrication facility dictates the size of the fabricated wafers, and any change in the wafer size will require costly accommodation to the change by the packaging facility.
Although it has been previously proposed to remedy this problem by forming interconnects from metals other than noble metals, this solution has not been satisfactory because of compatibility problems with the aluminum or aluminum alloys which form the metal pads on the semiconductor chips. For example, metals such as Pt and Pd cannot be formed on top of a pad made from Al or Al alloy without the formation of brittle intermetallic compounds between the two metals which can compromise the integrity of the electrical connection.